Device and material issues related to integration of junctions with contacts in deep 0.1 /spl mu/m MOSFETs

We address issues of process integration for source and drain (S/D) regions, which include formation of junctions and contacts for future scaled down MOSFETs. Computer simulation using Silvaco and material studies, were used to consider constraints originating in these regions and associated with both device operation and fabrication. In simulations, we focused on the role of doping profiles in the S/D regions on current drivability while devices are being scaled down to the sub. 0.1 /spl mu/m range. Fabrication and material analysis were oriented on shallow and heavy doped junctions produced using boride layers (TiB/sub 2/), which also acted as a contact material. High thermal stability of the stochiometric diboride ensures significantly restricted dopant outdiffusion to silicon during Rapid Thermal Processing. That should allow for high surface concentrations required for small contact and series resistance. Ohmic contacts are obtained for p-type wafers after annealing, while for n-type wafers, well defined non-leaky p-n diodes are formed. Techniques used in material studies (RBS, XPS and SIMS) did not reveal convincing dopant outdiffusion or significant changes in composition of the films.