Multi-valued flip-flop with neuron-CMOS NMIN circuits

In this paper, the implementation and verification of the fundamental flip-flops for the voltage-mode multi-valued logic circuits on a conventional CMOS VLSI chip are presented. Using the quantized NMIN circuits and the analog NMIN circuits, two types of the multi-valued R-S flip-flop are designed like a wide-use R-S flip-flop with NAND circuits and are applied to the D flip-flop for multi-valued memory. In verification through HSPICE simulation, the proposed flip-flops perform with good results such as high noise margins and low power consumption.