The word-level models for efficient computation of multiple-valued functions I. LAR based model

A new model of a multi-level combinational multiple-valued logic (MVL) circuit with no feedback and no learning is introduced. This model includes neuron-like gates (NLGs), each represents a level of the MVL circuit, so that the number of NLGs in the corresponding neural-like network (NLN) is equal to the number of levels in the circuit. The formal description of an NLG is a linear arithmetic expression (LAR) that is directly mapped to the linear word-level decision diagram (LDD) planar by its nature. Thus, an l-level MVL circuit is described by a set of l LDDs. The experiments on simulation of large MVL circuits show that the LDD format of an MVL circuit consumes 5-20 times less memory than EDIF and ISCAS formats. The proposed technique allows to simulate an arbitrary MVL circuit by an NLN and corresponding set of LDDs. In particular, we successfully simulated an NLN with about 250 NLGs corresponding to an MVL circuit with more than 8000 ternary gates that has been impossible by any recently reported threshold gate-based network.