Reuse issues on the verification of embedded MCU cores

The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included.