Evaluation of SCI as a fabric for a computer-based pattern recognition trigger running at 1.17 MHz

The future CERN experiment, LHCb, has the need for a high-speed first-level vertex trigger. The silicon vertex trigger of LHCb processes events at a rate of 1.17 MHz for a total of 3 GB/s of data. To handle this amount of data at the given rate, the plan is to build a cluster of approximately 250 nodes connected by a low-latency network. We have evaluated SCI as a possible candidate for this network. It is especially appropriate due to its low latency and overhead. The memory-mapped character of the connection makes it well-suited for applications relying on device-to-device copy mechanisms. We will present the results obtained with the Dolphin 66/64 PCI cards built around the PSB66 and LC3 chips. The behavior of two different topologies, two-dimensional (2-D) torus and ring, have been studied in detail. Results of DAQ/realtime relevant scenarios have been obtained using transport methods as programmed I/O, DMA, and device-to-device copy mechanism. Analysis of both hardware and software has been used to obtain a detailed picture of the traffic patterns on the buses involved.