Panel session - ESL methodology for SoC

While electronic system level (ESL) is being adopted in most electronic companies, there is still a need to explore and adopt new methodologies for early design development. Where there have been some successes in the areas of system analysis and virtual prototyping by SoC architects and software developers, investment costs for modelling can be costly or scarce. Also, there is yet to be a standard for applying IP power modelling that fits with a TLM terminology and into the overall system modelling process. Although power is hardly analyzed today even at the RTL level, “access” to power at the ESL domain may become much more critical, given the impact designers can have on power behaviour at this level. Ideally, software developers can also gain visibility into power dynamics and adjust their development flow to accommodate power guidelines, as well. With the current isolated HW and SW flows, this may seem unrealistic. What are some of the pitfalls of being “too early” in applying new technologies? This panel will explore critical issues and possible solutions for designing power applications, enabling engineering teams to rethink their approach to design planning using available ESL tools and methods.