Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124μA/μm and 1468μA/μm at off current of 1nA/μm for NMOS and PMOS, respectively.