Hardware Compilation from an RTL to a Storage Logic Array Target

This paper treats the automatic translation of register transfer level (RTL) descriptions of digital systems to VLSI realization. The target technology is the storage logic array or SLA. The approach is aimed at applications where the emphasis is on reducing engineering effort and design turnaround time rather than maximizing chip area utilization. The paper develops a mapping between the register transfer language, AHPL, and the SLA. It is shown that each primitive explicitly appearing in an AHPL description can be mapped into an area of real estate in an SLA realization. A detailed development of some of the algorithms is presented. The entire process has been successfully implemented and applied to a set of examples. This is accomplished by developing a final stage for an already existing three-stage multi-application compiler for AHPL. Layout and routing are shown to be a single optimization process if the hardware target is an SLA.