Digit-serial implementation of LDI/LDD allpass filters

In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serial computation has been shown to be advantageous compared to bit-serial and parallel arithmetics. The digit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period.