The realization method of SOC chip PAD automatic arrangement

With the continuous development of deep sub-micron technology, the design scale of integrated circuits is getting larger and larger, and more and more interfaces between SOC and the outside, which poses more challenges to the physical design of integrated circuits. For large-scale SOC, it requires a lot of work to place and route the PADs by manual, what’s the worse, this work can always be with high error rate. In order to solve this problem, an original physical design method which uses scripts to place the PADs is created to realize the automatic arrangement of complex SOC PAD. This method is suitable for any SOC with separated IO and PAD. The form and parameters of the scripts can be adjusted according to the specific process, so as to realize the automatic PAD arrangement, shorten the physical design period, and speed up the time to get into the market. This method has been applied in many products of the company, such as PLC chips, ADC chips, MCU chips, RFID chips, etc.