Improved Back Enhanced SOI (BESOI) MOSFET by adding n-doped regions

This paper reports the study of the Back Enhanced SOI (
^BE
SOI) MOSFET improvement through the inclusion of ndoped regions on the drain and source regions underlapped with the gate. This study was performed using TCAD Synopsys Sentaurus simulator. The main characteristic of the original
^BE
SOI MOSFET is the reconfigurable behavior, depending on the back-gate bias (V
GB
) the device can act as a p- or n-type transistor. However, the I
on
current is typically asymmetric. The proposed new structure by adding n-doped regions improves the drain current when the new
^BE
SOI is in the n-type
^BE
SOI configuration, which may take both transistor types to the same current level. The best results to L
MP
= 1 μm was obtained for V
GB
= |30| V, mainly when the transistor is in the triode region.