Impact of Sub-µm Wafer Thinning on Latch-up Risk in STCO Scaling Era

Extremely thin wafers are an important enabler for high density nano Through Silicon Via (nTSV) in future system-technology co-optimization (STCO) scaling. Measurements and TCAD simulations indicate that reducing the wafer thickness to 0.3µm is beneficial to latch-up prevention because of lower β-gain, which is induced by the strong recombination in well-base regions.