NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-µm BCD Process

The N-buried layer (NBL) causing low latch-up immunity between the HV-PMOS and LV-PMOS / LV-NMOS is studied in this work. The NBL layer has been often used to isolate the circuits from the common p-substrate for operating at different voltages, or to avoid noise coupling through the common p-substrate. As the HV circuits and LV circuits integrated together on the same silicon chip, the parasitic latchup paths between them would be easily triggered into a latch-up state under the current-trigger latch-up test. The latch-up or latch-up-like issues between the neighbor circuits with different power domains surrounding by NBL must be paid attention.