Implementing Multistage Interconnection Networks on FPGA Using Chisel Language

This paper discusses the utilization of the highly parametrizable Chisel language for FPGA designs. More specifically, the paper discusses the implementation of multistage interconnection networks (MINs) on an FPGA using Chisel. The MIN considered in this paper uses the well-known butterfly topology and a latency-insensitive design approach. The paper compares Chisel's performance against handcrafted VHDL, and demonstrates that Chisel simulation capabilities allows one to explore and study the behavior of a design in various situations. Our findings show that Chisel performs very well in both space and speed. Chisel's powerful testing capabilities revealed a limitation inherent to the MIN's architecture, and a cost effective solution is proposed.