Process Development and Failure Analysis of Super-Size Embedded Silicon Fan-out Package

With the rapid development of mobile consumer electronics, Internet of Things, 5G, artificial intelligence, new energy vehicles and other technologies, the demand for high integration, high performance, fast heat dissipation and miniaturization of electronic packaging is becoming more and more urgent. In this paper, based on the traditional embedded silicon fan-out (eSiFO) package with a package size of less than 5mm*5mm, we have developed a super-large eSiFO packaging technology, in which the package size is up to 30mm*40mm, the embedded chip size is up to 14mm*14mm, and the number of I/Os is as high as 1808. After completing the successful development of critical process such as cavity etching, die attaching, and vacuum lamination, the super-size eSiFO package we manufactured has an electrical yield rate of 96%, and has passed the electrical test in uHast- B 264 hours and TC-B 1000 cycles. Regarding the key technical problems in the super-size eSiFO package, a systematic study was launched and some practical optimization suggestions were provided.