Stress Analysis of Cu/Sn Bump Eutectic Bonding Interface

Cu/Sn wafer-level bonding is an interesting solution for wafer-to-wafer stacking technologies, due to its compatibility with 3D interconnections as well as vacuum sealing applications. The Cu/Sn eutectic bonding process is favored by industry and researchers alike for its excellent process compatibility and low cost, and has been proven for high density interconnect packaging of MEMS devices. Because of the presence of heterogeneous materials (TSV -Cu, Si substrates, Cu bumps, and Sn bumps) with large differences in coefficients of thermal expansion, the Cu/Sn interface exists varying degrees of stress and strain during the bonding process which can have an impact on the reliability of the bonding results. By optimizing the layout of the Cu/Sn bumps and the parameters of the bonding process, the stress and strain distribution during the bonding process can be reduced and the reliability of the Cu/Sn bonding interface can be improved. Based on ANSYS finite element steady-state thermodynamic analysis the stress and strain distribution at the bonding interface can be effectively obtained for different Cu/Sn bump layout, reducing the strain on the bump surface during the bonding process and improving the process reliability by optimizing the design rules.