Study on Warpage and Peeling Mitigation of Wafer Level During Metal Plating Process

Wafer level packaging is one of the latest trends in microelectronic packaging. Wafer warpage and metal peeling are common problem in wafer level packaging. Large warpage and large area peeling will cause the failure of post packaging and reliability problem. The mechanism of warpage and stress are the mismatch of material's coefficient of thermal expansion (CTE) and the change of temperature in the process. In this paper, after plating a metal layer on passivation (PA) layer, there is a large wafer warpage, which makes the following process unable to continue. Based on this background, plating a metal layer on the back side of wafer is innovatively proposed to overcome warpage. The warpage and peeling of back side metallization (BSM) are also measured. The experiment also compares warpage with and without BSM. The reason of peeling, the location of peeling and the interface of peeling were studied by experiments. Based on the finite element analysis (FEA). The effect of different BSM masks on warpage and peel stress were studied. The effects of local design and BSM thickness on peel stress are also studied. Through the research of this paper. It provides guidance for the metal plating process and design of BSM, and can effectively overcome the problem of wafer warpage and peeling.