A 22nm 10T FinFET SRAM Cell with Improved Write and Read performance in Sub-Threshold Region

Although voltage scaling presents an attractive alternative to overcome the issue of power consumption in the nanometer regime, it degrades the performance of static random access memories. This paper presents a 10T SRAM cell at 22 nm FinFET technology to achieve improved write and read performance in the sub-threshold region. A write assist transistor incorporated in the latch structure helps the node voltages to flip easily during a write operation and improve the write performance. In addition, the issue of high and data-dependent read bitline leakage is resolved by maintaining similar operating conditions in the read port of un-selected cells independent of stored data. This enhances the read bitline voltage swing compared to the other CMOS cells. The FinFET based design of the cell maintains a high read current in the read port and reduces read access time. Compared to the conventional 8T CMOS cell, the proposed design provides 19 %, 99.9 % and 70 % improvement in RSNM, read access time and read bitline voltage swing respectively at 0.3 V. Apart from significant improvement observed in write margin and write access time, an improvement of 17 % and 77 % are also noted in hold static noise margin and retention voltage in the sub-threshold region.