A clustering utility based approach for ASIC design

Due to the rapid growth of technologies, systems-on-chip (SoC) have started to become a key issue in today's electronics industry. In deep sub-micron designs, the interconnect is responsible for more than 90 percent of the signal delay in a chip. This paper presents a new approach for dealing with the high complexity of ASIC design. A new hierarchal clustering heuristic is presented that demonstrates excellent characteristics for reducing the execution time of standard-cell placement while achieving better results compared to non-clustered circuit placement methods. The clustering algorithm reduced the wire-length by 2% for small circuits and up to 10% for large circuits. Total execution time was reduced by more than 70% as expected.