Digital Predistortion Resource Optimization for Frequency Hopping Transceiver System

Frequency hopping (FH) is one of the best spread spectrum techniques for interference avoidance. Nonlinearity of PA is still a hindrance in using high efficiency modulation like QAM with FH. As dwell time is short, applying digital predistortion (DPD) to mitigate nonlinearity becomes critical. Memory Polynomial Model (MPM) based indirect learning architecture offers feasible solutions with reasonable resource utilization for FPGA implementation. Hard coded DPD in FPGA is the best possibility for FH system. It takes less time in the implementation and application of DPD. If a single DPD for the whole frequency band 105MHz (2.395GHz to 2.5GHz) is used, it will consume less FPGA resource but will not provide good result. Hard coded DPD at each hopping frequency is not possible because of limited resource of FPGA. So, a solution has been worked out to use six DPD, each DPD for 3 to 4 hopping frequency. Thus, this paper provides a real-time solution of DPD implementation for the FH system in the above band. NMSE has been used to judge the efficacy of DPD. The resource utilized and time taken has been studied in this paper.