CMOS implementation of the IDEA encryption algorithm

Describes the VLSI implementation of IDEA cryptochip using 0.25 /spl mu/m CMOS technology. With a new implementation of multiplication of modulo 2/sup 4/ + 1 (17), we achieved a high-throughput encryption and decryption. We present the functional verification and performance data using the IRSIM and HSPICE simulations.