FinFET LDMOS technology challenges and opportunities for digital TV and 6GHz WiFi PA applications

A comprehensive 12nm FinFET process-based LDMOS DC, RF, and extended reliability study is presented for the first time. To determine the optimal intrinsic device architecture, (i) an extended drain, (ii) dummy poly and (iii) STI LDMOS architectures were studied. The STI nLDMOS shows a higher breakdown (BV
dss
), lower C
gd
, higher F
max
and MSG (maximum stable gain) with lower HCI degradation among these three options. Moreover, the 3.3V STI nLDMOS delivers 1.84x of I
dsat
compared to previous node 22nm planar nLDMOS for comparable BV
dss
values. On the other hand, driving higher current through narrow silicon fins brings HCI reliability challenges. In response, the 5V nLDMOS was optimized for robust higher on-state voltage handling and reliability, while the 3.3V nLDMOS was configured for enhanced analog and RF performance. The 3.3V nLDMOS demonstrate an excellent RF F
t
/F
max
of 37.7/81GHz, MSG of 17.3dB performance with a robust ΔI
dsat
/ΔI
dlin
<10/20% HCI EOL performance.