Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

We report on scaled Si-channel finFETs (L
gate
>20nm, 45nm fin pitch) with backside connectivity enabled by: extreme wafer thinning (several Si thicknesses under STI-oxide targeted: from ~370nm down to ~20nm) and W-filled nano-through-Si-vias (n-TSV) of various heights (linked to wafer thinning values), after using low-temperature (LT), wafer-to-wafer (W2W) dielectric bonding. This scheme aims at allowing decoupling signal and power networks, with reduced IR-drop also predicted by moving the latter to the wafer’s backside. A thorough evaluation of the impact of 3D processing on device characteristics is presented, showing: 1) enhanced nmos mobility and drive currents (up to 15%); 2) for pmos, small I
ON
loss (~3 to 10%), larger R
ext
, with channel strain evaluation by NBD for various layouts; 3) ΔV
T~
-130mV that can be recovered with an extra anneal at the end, keeping tight variability and matching control. No BTI degradation is observed, with further indication that the final anneal(s) selection can be beneficial for electrostatics and reliability improvement.