Scaling synthetic WS2 dual-gate MOS devices towards sub-nm CET

We present a gate stack scaling study on dual gate (DG) WS
2
transistors with scaled back gate (BG) and top gate (TG) stacks using an ALD physisorption-seeding approach. DG MOSFET with a 2ML WS
2
and 100nm channel reaches 310µA/µm drain current, 320µS/µm max. transconductance at 1V Vd and sub-threshold swings of 69mV/dec and 116mV/dec at 0.1V and 1V Vd, respectively. With single charge centroid assumption, a 0.78nm DG and a 1.92nm TG CET are deduced. Statistics of 3000 FET demonstrates the performance trend and potential of EOT scaling on MX
2
MOSFET.