A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC

The ATLAS Tile Calorimeter (TileCal) readout link and control Daughter Board (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity Large Hadron Collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on- and off-detector electronics via bi-directional fiber optic links. Two CERN-developed, radiation hard GBTx ASICs receive LHC timing signals and configuration commands through 4.8 Gbps downlinks, which are in turn propagated to the front-end through Xilinx Kintex Ultrascale FPGAs. The Kintex FPGAs also continuously perform real-time readout and transmission of digitized PMT samples, Detector Control System signals and monitoring data through redundant pairs of 9.6 Gbps uplinks. The DB design aims at minimizing single points of failure, and improving performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified COTS components. Mitigation of radiation-unduced Single Event Upsets (SEU) in the FPGAs is performed by a combination of the Xilinx Soft Error Mitigation (SEM) utility and Triple Mode Redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through Forward Error Correction (FEC) in the downlinks and Cyclic Redundancy Check (CRC) error verification in the redundant uplinks. This paper presents the latest revision of the DB (version 6), a redesign that addresses unexpected Single Event Latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the ADC read-out, and improved timing performance.