Self-Regulated Clock Distribution Network for a Fast-Timing Active Hybrid Single Photon Detector

Time resolution of active pixel sensors whose time stamp mechanism is based on Time-to-Digital Converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The Clock Distribution Network that delivers the master clock signal must be robust to the non-idealities of the electronics, mainly process-voltage-temperature variations, device and layout mismatch and noise coupling to minimize static time errors and jitter. In order to achieve sub-100ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the resolution in the adjustment of the network propagation delays or latencies must be well below that value. In this work, a self-regulated Clock Distribution Network that is robust to static and dynamic time errors is presented for the FastICpix hybrid single photon detector - aiming at a 65nm process. A 40 MHz clock is distributed to 64×64 pixels over an area of 2.4×2.4 cm
²
using digital Delay-Locked Loops. The latency from the clock source to the nodes of the network can be adjusted in steps finer than 20 ps, which is essential to enable a single photon time resolution of this order.