Process optimization of micro bump pitch design in 3-dimensional package structure

CoW using TSV technology has been suggested for process flexibility with high bandwidth in wafer level process (WLP). To connect I/O terminals, Thermo-compression process is generally used with using of non-conductive film (NCF). Although TC-NCF can suppress inner void and have a high production efficiency, solder sweep phenomenon, one of device fail reasons between signal bumps, was reported. This paper focus on design for three dimensional packaging technology and discuss optimal bonding process, NCF material and bump array design. TC-bonding simulation is also adapted for increasing experimental accuracy. The simulation is successfully estimated a sweep behavior and well matched with actual experimental results. It is expected that I/O counts per unit area is be expected to increase about 4 times and flexibility of I/O layout was also ensured.