Fine Pitch Line/Space Lithography for Large Area Package with Multi-Field Stitching

Growth in the usage of heterogenous integration and chiplets-based designs in modern advanced packages for leading applications like AI and HPC is driving the need for very large chip sizes that exceed the dimensions of a single back-end stepper exposure field. Simultaneously, these advanced designs are requiring 1.0 micrometer or smaller linewidth connections in their redistribution layers to meet their package I/O density and bandwidth performance requirements. In this paper, we demonstrate a process for 1.0 and 0.8 micrometer Cu lines across a two-field stitch boundary, and tests indicate negligible impact of the stitch on electrical resistance or leakage current. We show that this process is viable to support fine resolution features for large area packages.