Reliability of Chip-Last Fan-Out Panel-Level Packaging for Heterogeneous Integration

In this study, the reliability of the solder joints of a heterogeneous integration of one large chip and two smaller chips by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a panel is investigated. Emphasis is placed on the thermal cycling test (
$-55^{\circ}\mathrm{C}\rightleftarrows 125^{\circ}\mathrm{C}$
, 50-minute cycle) of the heterogeneous integration package on a PCB (printed circuit board). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A non-linear, time and temperature dependent 3D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.