Chip/Package Co-Design Analysis of Advanced D2D Interface Using a Statistical Link Simulator

As the market for display technologies such as 4K, 8K and above, fifth generation (5G) communications and artificial intelligence (AI) grows, the demand for high-speed and low-power I/O interfaces is increasing. At the same time, I/O area is a major design factor for these systems, so it is important to not to overdesign I/O interface and to find the balance of design resource and performance. In case of advanced packaging systems such as System-in-Package (SiP), and Die-to-Die (D2D), etc., chip-to-chip interface has increased chip portion in the overall system due to a large number of I/Os and the short channel length. Such interfaces designs, characteristics of both on- and off-chip, even their interactions should be considered to accurately predict system specifications. Also, performance prediction in an early design stage and tracking the design performance during various design stages are crucial to the success of advanced SiP designs. SPICE simulation which is commonly used for on-chip and off-chip level jitter analysis perhaps has the highest accuracy for performance prediction, but is inefficient to use in the early design stage because of its long simulation time and complex modeling. Statistical simulation that quickly predict low BER numbers at the system level can be a good alternative. In this paper, using statistical link simulator that can be applied from the initial design stage, the codesign of chip and package is applied to advanced D2D interface. In-house developed simulator which models various jitter components and on-chip timing paths is introduced. We present the overview of the simulator algorithm and the co-design flow using an advanced D2D interface design. On-chip jitter model and tracking of the data path jitter with forwarded clock is demonstrated.