Fin-TFET: Design of FinFET-based Tunneling FET with Face-tunneling Mechanism

A novel low voltage FinFET-based tunneling FET (Fin-TFET) with face-tunneling mechanism and Ge/SiGe material is proposed in this paper. The proposed device structure enhances the on-state drive current at low V
dd
and also provides lower off-state leakage current, steeper sub-threshold slope, higher I
on
/I
off
ratio, and smaller parasitic capacitance compared to the other TFETs. These advantages are attributed to a larger tunneling area and proper use of the SiGe-channel, i.e., the suppression of the leakage current, and the channel region with small bandgap Ge which can enhance the tunneling current. Furthermore, a novel hybrid 6T SRAM is proposed and verified to reduce the read disturb and enhance the RSNM/WSNM of SRAM.