Low-Latency BCH-CRC Decoder for 3D CT NAND Flash Memory Applications

This paper presents a low-latency BCH-CRC decoder for 3D CT NAND flash memory. The presented decoder uses the hard-decision values as the input, which can avoid the energy-consuming sensing operations for generating the soft-decision values and hence extend the life time of flash memory. In order to improve the error correction performance, a BCH-CRC concatenated coding scheme is developed. Moreover, the BCH decoding algorithm is optimized to reduce the overall cost of the decoder. We implement the proposed decoder targeting at 3D CT NAND flash memory applications. The user data length is 512 bytes, which is divided into four segments. A 16-bit CRC is appended to each segment, and then the message sequence is encoded by a BCH code with 9-bit error correction capacity. The decoder is realized in a 65nm CMOS process, which can achieve a decoding throughput of 191MB/s with latency 2.795µs.