A 1ps Resolution Two-Step Time-to-digital Converter Using Parallel Digital-to-time Converters

A two-step time-to-digital converter (TDC) based on digital-to-time converter (DTC) is proposed in this paper. This architecture uses DTC as delay cell, it changes DTC's delay time by adjusting the DTC's delay control words(DCW) , and sets the neighboring DTC's delay time to keep the TDC's resolution constant. The resolution can reach 1 picosecond. Two-step structure can reduce the number of flip-flops and delay cells by half, it can reduce the power consumption significantly, and the area is also decreased at the same time. This 4-bit TDC architecture has been designed and simulated in 130nm CMOS process. The power consumption is about 0.7mW; the resolution is 1 picosecond and the core area is about 0.017mm
²
.