A Compact & Low Power Architecture of XXTEA192 Lightweight block cipher

RFID and IoT security threats have been increased due to the enormous usage of ubiquitous computing devices. Providing security to RFID tags is one of perplexing tasks as it has to meet rigid area and power requirements. This paper has proposed a compact serial architecture for XXTEA-192 block cipher which can be used in RFID applications. The RFID tags are constrained with limited area and power. XXTEA is the most secured version among the ciphers of TEA family. This cipher works on variable length message with a minimum message length of 62-bit and should be a multiple of 32-bit words. This feature enables the cipher to encrypt larger block sizes. Serial architecture of XXTEA-192 has been proposed that performs 32-bit operations like addition, XOR and shifting in each clock cycle. The proposed design has been implemented using verilog. Analysis of performance metrics like area, throughput, efficiency, power and energy has been performed on different families of FPGA devices like Spartan 6, Virtex 6 and Virtex 7. The proposed design has achieved 45 slices and a throughput of 498.44 Mbps on Spartan 6 making the architecture area and speed efficient for RFID applications.