Integration Process for Self-aligned Sub-µm Thin-Film Transistors for Flexible Electronics

Thin-film transistors (TFTs) enable low-cost integration of electronic circuits. Due to the low thermal load during manufacturing, flexible substrates can be used, making TFTs suitable for flexible electronic applications such as RFID labels or diagnostic sensors. To achieve mass applications, an increase in the performance of TFTs is required. In this context, the transit frequency f
T
is an important indicator. This frequency is influenced not only by the charge carrier mobility but also by the overlap of the gate electrode with the drain/source electrodes and by the channel length [1]. For realistic mobilities of about 10 cm
²
/ Vs and low operating voltages (V
D
≤ 10 V), channel lengths in the submicrometer range are required for transit frequencies in the megahertz region [2]. In this work, we report on an integration routine for TFT fabrication in the submicron range by combining a dry etching process for structuring the gate electrode with a self-alignment process for patterning the drain/source electrodes. The self-alignment also minimizes the overlap between the gate and the drain/source electrodes, thus reducing the parasitic capacitances.