Silicon Wafer Uniformity and Roughness Control by Etchants on Wafer Thinning

In order to improve the electric capacity and thermal diffusivity on different types of power devices (DMOS, SJ, SGT, IGBT, etc.), the industry is always looking for better uniformity and suitable roughness from backside wafer thinning before metal deposition. After mechanical grinding, the silicon crystal lattices are dislocated and distorted. Chemical etching is used to remove the silicon layer damaged from grinding. In this paper, we use two spin etch steps to improve wafer uniformity and use the different parameters (temperature, flow rate, process time, chuck speed) of another spin etch step to achieve the roughness requirement. Finally, we can also add etchants to lower our Ra (roughness) to meet special production requirements.