Exploration of PFSCL in Subthreshold region of operation for use in ultra low power applications

This paper presents the implementation of digital logic using positive feedback source coupled logic (PFSCL) style operating in subthreshold region, for use in ultra low power applications. Subthreshold PFSCL (STPFSCL) divide-by-8 circuit has been designed and simulated using PTM 90nm CMOS technology and found to have PDP of 0.4pJ compared to a PDP of 2.96pJ for ST-CMOS. Further, in ST-PFSCL, the delay depends on the bias current and not on the power supply, thus providing added flexibility to the design of ultra low power applications. Implementation of ST-PFSCL gates has been explored through XOR2 using both traditional NOR based and stacked transistors in the pull down network, leading to multistage and single stage implementation respectively. The single stage implementation of ST-PFSCL XOR2 provides a PDP of 0.006pJ and an improvement by a factor of 8.33 in frequency of operation for a given power dissipation and a reduction in power dissipation by a factor of 7.5 for a given frequency of operation in comparison to ST-PFSCL NOR based implementation.