Influence of High-k Oxide Thickness on Gate Stack DMG Junctionless SOI MOSFET

The present paper describes the influence of Gate stacking on Dual Material (DM) Junctionless (JL) SOI MOSFET operating in Junction Accumulation Mode(JAM). The performance of the proposed MOSFET structure, simulated with 2D ATLAS device simulator, is investigated for variations in thickness of the high-k (HfO
₂
) Gate oxide. The analog performance of the DMG JL JAM SOI MOSFET is examined on the basis of its transfer characteristics, transconductance, transconductance generation factor, Drain induced barrier lowering(DIBL), I
_ON
/I
_OFF
ratio and gate capacitance variations with the gate voltage. Its cut-off frequency is also studied. In addition, a single stage amplifier based on the proposed MOSFET is simulated and its response is studied for the variations in high-k oxide thickness. The simulation results reveal that reduction in the high-k oxide thickness improves the device performances.