Analysis of Drain Current Enhancement in "PN-Body Tied SOI-FET" -Bulk vs Surface Conduction Mode and Low Vds Saturation Effect-

We have proposed "PN-Body Tied SOI FET (PNBT-FET)" as a candidate of steep subthreshold slope (SS) devices, such as tunnel FETs and negative capacitance FETs, which will be a key device for expanding ultralow power IoT applications. We have already reported that PNBT-FET has SS below 1mV/dec over several orders of the drain current even with ultralow drain voltage of 0.1V [1] - [2] . We also reported the drain current (Id) enhancement effect on PNBT-FET, at previous IEEE SNW [3] .