Approximate Multipliers for Optimal Utilization of FPGA Resources

Approximate or inexact arithmetic is a promising approach towards lower power consumption for applications that can tolerate a certain amount of imprecision. As human perception is limited in its precision, this applies to image and audio processing. Beyond, other applications like neuronal networks or AI processing can benefit from such arithmetic as well, as they are inherently tolerant to a certain amount of inaccuracy. One of the most critical components of arithmetic circuits regarding power, delay, and area are multipliers. Various sophisticated approaches towards approximate multipliers are already published for ASICs. However, such ASIC approaches are under-performing in conjunction with the specific Lookup-Table (LUT)-based design of FPGAs. As FPGAs gain in importance for applications like signal processing, there is a substantial lack of approximate design methodology for FPGAs. We propose an approach towards approximate signal processing that is specifically tailored towards the LUT-based hardware of FPGAs. It allows for significant performance improvements while lowering the energy demands. While introducing an insignificant average relative error of just 0.14%, we achieve a 45.9% area reduction in terms of LUTs while decreasing the delay by 30.6% compared to the Xilinx Vivado multiplier IP core. Our proposed design is open source and available at https://github.com/niemann-c/approx-mult-for-fpga.