Improving Pathfinder Algorithm Perfomance for FPGA Routing

The paper presents some algorithmic improvements to accelerate the routing stage for FPGA. One of the main advantages of FPGA is the high development speed; thereby the importance of efficient computer-aided design tools for modern FPGA is hard to overestimate. The placement and routing stages are crucial for the FPGA performance, and meanwhile they take up a significant part of the design time. The investigated base routing algorithm is the modified Pathfinder for the mixed routing resources graph. Pathfinder is a popular iterative negotiation-based router acting on the principle of eliminating nets congestions. Due to the proposed algorithmic improvements, such as ignoring the uncongested nets while rip-up and rerouting stage, and some other, the summary routing time is reduced significantly. The observed average time decrease is from 1.3X to 2.6X depending on the FPGA architecture. The benchmarks ISCAS'85&89, LGSynth'89 and several real industrial circuits were used for testing.