Research on visualization planning method of distribution network based on graphical model integration

High efficient video coding (HEVC) is a new video coding compression standard. HEVC adopts context-based adaptive binary arithmetic coding (CABAC) as the entropy coding scheme. In this paper, the overall architecture and efficiency of the main frequency are improved by the optimization of the input and output modules and the module optimization of the arithmetic coding CABAC hardware structure. In terms of input module optimization, four-level buffer input and residual coefficient transmission optimization are adopted; in terms of arithmetic coding module optimization, context model index pre-reading, pre-normalization look-up table and in-line serial stream output design are adopted so as to improve the overall efficiency of the architecture and the main frequency, reduce resource consumption, and achieve a high-frequency hardware architecture of the efficient coding pipeline. The combined results show that the pipeline can operate at 370MHz with 43.49K gates aiming at 90nm process. The processing rate and throughput can support real-time encoding of 1080P video under the general test conditions of the HEVC standard of 30 frames per second.