Power Estimation of FIR Filter based on IP Modeling for DSP and Communication Applications

Nowadays, the main focus is on power estimation at higher abstraction level but that would be estimated at the cost of low accuracy. This is because at higher abstraction level most of the lower-level information is missing. So, power estimation at Register Transfer Level (RTL) in an early design cycle can be an attractive alternative to achieve better accuracy. Finite Impulse Response (FIR) filter is the critical block in many Digital Signal Processing (DSP) and Digital Communication applications exclusively for computationally intensive tasks that consumes more power. Therefore, in this paper, 4-tap FIR filter have been designed using IP modeling approach at RTL level in which some embedded Intellectual Property (IP) and some user defined IPs are used. Power estimation model for different modules of FIR filter have been developed based on curve fitting and regression technique using MATLAB R2018a. Accuracy of each model has been validated against the power obtained from Vivado 2014.2 tool targeted to Zynq family Field Programmable Gate Array (FPGAs) device (xc7z020clg484-1). Finally, estimated power of each IP core through model has been used to estimate the power of a complete FIR block using the methodology proposed by David Elleouet et al. in their paper. The estimated power of a complete FIR block is also validated against the estimated power obtained using commercial tool (Vivado). It has been observed from the analysis that the power estimation methodology based on IP modeling proposed by David Elleouet et al. requires reconsideration as it is providing high deviation in power estimation values for FIR filter.