Vector-Qubit models for SoC Logic-Structure Testing and Fault Simulation

A new technology for the synthesis and analysis of vector-driven gate- and RTL-logic based on the test equation metric, which forms the xor-relations between test, function and faults, is proposed. A vector form for describing structures is presented, which makes it possible to apply the technologies developed by scientists for the synthesis and analysis of logical circuit tests to effectively solve the problems of testing graph structures and automaton models of digital devices. The main problems of technical diagnostics (test synthesis, device model development, fault analysis) are defined as relation derivatives of the testing equation. The notion of X-function is introduced to measure all processes and phenomena in the digital world; it is a function that cannot be modified and/or minimized. A qubit-vector test synthesis method based on the derivatives calculated by vector coverage of logic is presented. Estimates of the computational complexity of the synthesis of tests and deductive formulas for logic and their use in fault simulation are given.