Heuristics for Order-Lot Pegging In Multi-Fab Settings

In this paper, we study order-lot pegging problems in semiconductor supply chains. The problem deals with assigning already released lots to orders and with planning wafer releases to fulfill orders if there are not enough lots. The objective is to minimize the total tardiness of the orders. We propose a mixed integer linear programming (MILP) formulation for this problem. Moreover, we design a simple heuristic based on list scheduling and a biased random key genetic algorithm (BRKGA). Computational experiments based on problem instances from the literature for the single-fab case and newly proposed instances for the multi-fab setting are conducted. The results demonstrate that the BRKGA approach is able to determine high-quality solutions in a short amount of computing time.