Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium

The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with respect to the stacked-via configuration. SV first and SV last integration approaches were electrically tested using full barrierless ruthenium (Ru) on a dielectric low-k 3.0. A maximum AR = 3.8 was achieved with ~2.4 times lower resistance than the alternative stacked-via configuration. Thermal shock tests produced no SV failure after 1000 cycles between -50 °C and 125 °C, and 250 hours. Time-dependent-dielectric-breakdown (TDDB) tests between SV and M2 lines gave a TTF
63.2%
(at 1 MV/cm) > 10 years, when 3 M2 tracks are blocked.