Sub-ns Polarization Switching in 25nm FE FinFET toward Post CPU and Spatial-Energetic Mapping of Traps for Enhanced Endurance

In this work, we report sub-ns polarization switching in highly scaled 25 nm ferroelectric (FE) FinFET with Hf
0.5
Zr
0.5
O
2
(HZO) ferroelectric (FE)/SiO
2
dielectric (DE) gate stack for high performance CPU application for the first time. Observed limited endurance was attributed to the increase of trap density in the stack, which was quantitatively analyzed upon program/erase cycles by various methods including newly adopted low-frequency noise (LFN) characteristics for resolving spatial and energetic distribution of traps. In particular, we identified three different types of traps at FE/DE interface (D
it_2
) and SiO
2
/Si channel interface (D
it_1
) as well as in the bulk oxide (N
ot
) of the HZO/SiO
2
gate stack of FE FinFETs. In addition, with the developed trap analysis, we investigated radiation-induced degradation of HZO/SiO
2
gate stack for application under harsh environments. Highly scaled and high performance FE FinFETs with enhanced endurance would provide a viable solution for future platform of low-power computing.