Evaluation Method of CMOS Devices Reliability at Cryogenic Temperature Based on SSI Model

With the development of deep-space exploration, electronic components and integrated circuits in the spacecraft must face the harsh environment in deep space, including cryogenic temperature. For CMOS devices, cryogenic temperature may cause issues in reliability. To qualify the normal application of CMOS devices, an evaluation method of CMOS devices at cryogenic temperature based on stress-strength interference theory was proposed. Moreover, according to the method, stress-strength interference models were built to calculate the failure probability of SN74AHC14 CMOS Inverters at cryogenic temperature.