Evaluation of Modified Collaborative Triple Module Redundancy Based on COTS Heterogeneous Processor

For the Commercial-Off-The-Shelf (COTS) heterogeneous processors are sensitive to single event upset (SEU), we brought up the collaborative triple module redundancy (CTMR) to improve the SEU mitigation ability. However, the early stage CTMR is poor at real-time performance and the new architecture FPGA voter within heterogeneous processor hasn't been evaluated. Thus, we combine ECC, two-level cascade interrupt and other technique to improve the real-time ability and employ precise Read-Modified-Write fault injection method to evaluate the FPGA. According to the simulation of SEU injection, the run time decreases nearly 3 orders of magnitude and the reliability rate of the voter increases 13.9%. The analysis of FPGA structure can provide guidance for accurate fault injection, and COTS heterogeneous processor with system-level reinforcement can provide a new option for the chips' selection of low orbit microsatellite.