Customized Layout Method of SRAM Bit cell for Body tie in Nanoscale Technology

In nanometre scale process, the modification of the SRAM bit cell layout provided by foundry to add body-tie to improve the reliability may affect the yield of SRAM IP, and this modification is not supported by foundry. For this situation, this paper proposed the bit cell continuation method with small area overhead which improves the density of body-tie. Based on 65nm bulk CMOS process, test chip was designed and tape-out. The tested results show that this method has advantage of small speed, power, yield and area cost. It can be used in the design of SRAM IP fabricated by 90nm and below process to stabilize the body region of transistors in SRAM array and improve the reliability of SRAM IP.